This invention relates generally to static memory devices. Particularly, this invention relates to a high density Static Random-Access Memory (SRAM) cell taking advantage of the latch-up phenomenon in a Complementary Metal Oxide Semiconductor (CMOS).
There are two major types of random-access memory cells, dynamic and static. Dynamic random-access memories (DRAMs) can be programmed to store a voltage which represents one of two binary values, but require periodic reprogramming or xe2x80x9crefreshingxe2x80x9d to maintain this voltage for more than very short time periods. Static random-access memories (SRAMs) are so named because they do not require periodic refreshing.
SRAMs are bistable, meaning that they have two stable or self-maintaining operating states, corresponding to different output voltages. Each operating state defines one of the two possible binary bit values, zero or one. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a xe2x80x9chighxe2x80x9d voltage to indicate a xe2x80x9csetxe2x80x9d operating state, usually representing a binary value of one, and produces a xe2x80x9clowxe2x80x9d voltage to indicate a xe2x80x9cresetxe2x80x9d operating state, which usually represents a zero. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback mechanisms that maintain a stable output voltage, corresponding to the operating state of the memory cell, as long as the memory cell receives power.
The operation of a static memory cell is in contrast to other types of memory cells such as dynamic cells which do not have stable operating states. A dynamic memory cell requires periodic refreshing to maintain storage of a voltage for more than very short time periods, because it has no internal feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift toward intermediate or indeterminate voltages, resulting in loss of data. Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the six transistors typically required in a static memory cell.
Conventional CMOS SRAM cells essentially consist of a pair of cross-coupled inverters as the storage flip-flop or latch, and a pair of pass transistors as the access devices for data transfer into and out of the cell. Thus, a total of six Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), or four MOSFETs plus two very high resistance load devices, are required for implementing a conventional CMOS SRAM cell. The large number of devices required for each CMOS SRAM cell results in exceptionally large cell areas, typically over 100F2, where F is the minimum feature size. Even using only n-channel devices, cell size in a compact SRAM design is commonly over 50F2. See U.S. Pat. No. 5,486,717. The result is much lower densities than for DRAMs, where the cell size is only 6 or 8F2.
To achieve higher packing densities, several methods are known for reducing the number of devices needed for CMOS SRAM cell implementation, or the number of the devices needed for performing the Read and Write operations. However, increased process complexity, extra masks, and high fabrication cost are required and the corresponding product yield is not high.
For example, K. Sakui, et al., xe2x80x9cA new static memory cell based on reverse base current (RBC) effect of bipolar transistor,xe2x80x9d IEEE IEDM Tech. Dig., pp. 44-47, December 1988), refers to a Bipolar-CMOS (BICMOS) process in which only two devices are needed for a SRAM cell: one vertical bipolar transistor, and one MOSFET as a pass device. Extra processing steps and increased masks are required, along with special deep isolation techniques, resulting in high fabrication cost and process complexity. Yield of SRAM products utilizing such complex processes is usually low compared with the existing CMOS processes.
A problem with CMOS circuits in general is their propensity to xe2x80x9clatch-up.xe2x80x9d Latch-up is a phenomenon that establishes a very low-resistance path between the VDD and VSS power lines, allowing large currents to flow through the circuit. This can cause the circuit to cease functioning, or even to destroy itself due to heat damage caused by high power dissipation.
The susceptibility to latch-up arises from the presence of complementary parasitic bipolar transistor structures, which result from the fabrication of the complementary MOS devices in CMOS structures. Because they are in close proximity to one another, the complementary bipolar structures can interact electrically to form device structures which behave like p-n-p-n diodes. In the absence of triggering currents, such diodes act as reverse-biased junctions and do not conduct. Such triggering currents, however, may be and in practice are established in any one or more of a variety of ways, e.g., terminal overvoltage stress, transient displacement currents, ionizing radiation, or impact ionization by hot electrons.
Gregory, B. L., et al., xe2x80x9cLatch-up in CMOS integrated circuits,xe2x80x9d IEEE Trans. Nucl. Sci. (USA), Vol. 20, no. 6, p. 293-9, proposes several techniques designed to eliminate latch-up in future CMOS applications. Other authors, such as Fang, R. C., et al., xe2x80x9cLatch-up model for the parasitic p-n-p-n path in bulk CMOS,xe2x80x9d IEEE Transactions on Electron Devices, Vol. ED-31, no. 1, pp. 113-20, provide models of the latch-up phenomenon in CMOS circuits in an effort to facilitate design optimizations avoiding latch-up.
The present invention takes advantage of the normally undesirable latch-up phenomenon in CMOS circuits to construct a compact static memory cell.
The present invention provides area efficient static memory cells and memory arrays by the use of parasitic bipolar transistors which can be latched in a bistable on state with small area transistors. Each bipolar transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. These cells can be realized utilizing CMOS technology to create planar structures with a minimum of masking steps and minimal process complexity.
Advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.